6.3 SSC Receiver

The SSC receiver block is designed with three main parts, namely the receive clock controller, the start selector and the receive shift register.

The receiver block is fed with three different clock sources as listed below, one of which will be selected by the receive clock controller as the receiver clock.

  1. Clock from the RK pin (RK pin is an input).
  2. Clock from the SSC clock divider.
  3. Clock from the transmitter block.

The start selector controls when a receive frame has to be started in the receiver block. The frame start event is configurable and can be one of the events below.

  1. Start frame with receiver enabled (RXEN). This is a Continuous mode operation where data is received immediately after the end of the transfer of the previous data, provided RXEN is set.
  2. Start frame on event trigger from the transmitter’s start selector (TX Start).
  3. Start frame on RF event. The RF event can be low level / high level / any level change / rising edge / falling edge / any edge.
  4. Start frame on compare match of incoming bit pattern with bit pattern in the SSC_RC0R register.

The receive shift register is used to receive the serial data. An SSC frame can have sync bits received before the actual data is received on the RD pin. Two registers are used for this purpose, namely SSC_RHR (to hold the actual data) and SSC_RSHR (to hold the sync bits). If configured and enabled, the sync bits are received first, followed by the actual data. The sync bits can be either a fixed logic level for a given number of bit cycles or a bit pattern.