6.4 SSC Frame Format

The data framing format of both the transmitter and the receiver is programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select the following parameters:

  • Event that starts the data transfer (START)
  • Delay, in number of bit periods, between the start event and the first data bit (STTDLY)
  • Length of the data (DATLEN)
  • Number of data to be transferred for each start event (DATNB)
  • Length of synchronization transferred for each start event (FSLEN)
  • Bit sense: most significant bit first (MSBF)

    MSBF = 1: MSB sent first

    MSBF = 0: LSB sent first

Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and the Data Default Value (DATDEF) bits in SSC_TFMR.

The figure below shows the frame format of an SSC frame.

Figure 6-2. SSC Frame Format

An SSC frame start is triggered by the start event generated by the start selector and begins transmitting/receiving the sync data on the TD/RD pins. The sync pulse and the sync data are available on the bus for FSLEN bit cycles. The sync data will be the configured value of SSC_TSHR if FSDEN = 1 or will be the configured default level (value of the DATDEF bit) if FSDEN = 0.

In a transmitter with FSDEN = 1, once the FSLEN bit cycles are passed, the configured default logic level is sent on the TD line for (STTDLY – FSLEN) bit cycles if STTDLY > FSLEN. If STTDLY < FSLEN, the remaining sync data will not be sent, but the actual data will be sent, so such a configuration should be avoided.

In a receiver with FSDEN = 1, once the FSLEN bit cycles are passed, the RD line will not be sampled for (STTDLY – FSLEN) bit cycles if STTDLY > FSLEN. If STTDLY < FSLEN, the remaining sync data will be sampled as actual data, so such a configuration should be avoided.

Once the STTDLY bit cycles are passed, the actual data transmission/reception starts. The data length for each word can be defined in the DATLEN field, and the number of words in each frame can be defined in the DATNB field. The sync pulse can be generated periodically every (2 * (PERIOD + 1)) bit cycles.

If the frame size PERIOD > (STTDLY + (DATNB * DATLEN)), then for the remaining bit cycles:

  • In the transmitter, the default logic level defined by DATDEF will be sent on the TD pin.
  • In the receiver, the RD bits will be ignored.

The table below shows the bit fields and registers used to construct an SSC frame with their maximum lengths.

Table 6-1. SSC Transfer Parameters with Respective Bit Lengths
Transmitter RegisterReceiver RegisterField

Length

(no. of bits)

Comment

SSC_TFMR

SSC_RFMR

DATLENUp to 32Size of a word
DATNBUp to 16Number of words in a frame
MSBF-Most Significant Bit First
FSLENUp to 256Size of sync data register
-DATDEF0 or 1Data default value ended
-FSDEN-Enable send SSC_TSHR

SSC_TCMR

SSC_RCMR

PERIODUp to 512Frame size
STTDLYUp to 255Size of transmit start delay

Note that from the above table, up to 256 bits can be allotted for FSLEN. However, the FSLEN is just 4 bits in SSC_TFMR / SSC_RFMR. The 4-bit FSLEN is used along with a 4-bit field FSLEN_EXT in the same register so that the total FSLEN slot can accommodate 256 bits. The pulse length is calculated as:

FSLEN + (FSLEN_EXT * 16) + 1 clock cycle

When FSDEN is set to 1, the frame synchronization data from SSC_TSHR is sent for FSLEN cycles. However, SSC_TSHR is only 32 bits in length, so synchronization data of more than 32 bits is sent in the following order:

  1. SSC_TSHR (32-bit)
  2. DATDEF (32-bit)
  3. SSC_THR (32-bit)
  4. Repeat SSC_THR until 256 bits are reached.