6.5 Code Examples

The code example given in this section demonstrates the steps to play back a 48 kHz stereo 16-bit PCM audio using the SSC interface and an external audio DAC IC (AD1934 from Analog Devices).

The 12.288 MHz master clock is generated from the Audio PLL as described in section Code Example - Audio PLL. The generated 12.288 MHz signal from the CLK_AUDIO pin is fed to the MCLKI pin of the AD1934. The AD1934 is configured to generate the bit clock and the LR clock with a sample rate set to 48 kHz. The word width of the AD1934 is always 32 bits and is configured to accept audio data in I2S frame format and left-justified with MSB first. The following are the register settings for the AD1934, which is configured using the SPI interface.

• PLL and Clock Control 0 --> 0x98
• DAC Control 1 --> 0x70
• DAC Control 2 --> 0x18

The other AD1934 registers are left at their default reset values.

The following sections provide the code snippet to configure the SSC I/O pins, the DMA channel and the SSC peripheral.