6.1 SSC Clock Divider

The SSC has an internal clock divider that takes the peripheral clock (MCK from PMC) as its input and divides the clock with a fixed divide-by-2 divider, followed by a configurable divider with a maximum division factor of 4095 (12-bit divider).

The overall division factor of the clock divider is 8190. Each level of the divided clock has a duration of the peripheral clock period multiplied by DIV. This ensures a 50% duty cycle for the divided clock, regardless of whether the DIV value is even or odd.

The divided clock can be input to both the transmitter and the receiver blocks.

Note: There is a limitation for the bit clock frequency when SSC is operated in Slave mode. When SSC is operated in Slave mode, the MCK frequency must be greater than (6 * bit clock frequency). For an MCK frequency of 166 MHz (maximum for SAMA5D2), the maximum bit clock frequency can be approximately 27.666 MHz.