1.11.1 MIPI RX

The MIPI RX is supported only in GPIO Bank. The corresponding Bank voltage (VDDI), and VDDAUX voltage must be connected as shown in the following figure.

Figure 1-9. MIPI RX Connection

MIPI RX signal connections are as follows:

  • Four data and clock must be within one DDR_Lane.
  • Connect the data signals to adjacent DDR_Lanes, if more than four data signals are available.
  • The MIPI RX clock must be connected to a CLKIN pin.

For more information about DDR_Lane, see PolarFire SoC Packaging Pin Assignment Table.