1.11.2 MIPI TX

The MIPI Low Power (LP) signals should be connected to a 1.2V GPIO/HSIO Bank supply. High-speed signals should be connected to a 2.5V GPIO Bank supply. Select the HS and LP pins in adjacent pins to minimize the LP stub. The HS data and clock signals should be in one DDR_Lane. For more information about DDR_Lane information, see PolarFire SoC Packaging Pin Assignment Table.

The MIPI TX standard can be implemented by using the resistor divider network for Low Power (LP) and High Speed (HS) signals, as shown in the following figure. The resistor values mentioned in the following provide a throughput upto of 1 Gpbs.

Figure 1-10. MIPI TX Connections
Important: Run the PDC verification in the Libero SoC tool before moving to layout. To know about MIPI RX electrical characteristics, see PolarFire SoC Datasheet.

For information about the MIPI layout guidelines, see MIPI.