13.6.8.10 APBB Mask

Name: APBBMASK
Offset: 0x18
Reset: 0x00000017
Property: PAC Write-Protection

Bit 3130292827262524 
 Reserved[28:21] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 Reserved[20:13] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 Reserved[12:5] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 Reserved[4:0]NVMCTRLDSUUSB 
Access RRRRRR/WR/WR/W 
Reset 00010111 

Bits 31:3 – Reserved[28:0] Reserved bits

Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0.

Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable

ValueDescription
0The APBB clock for the NVMCTRL is stopped
1The APBB clock for the NVMCTRL is enabled

Bit 1 – DSU DSU APBB Clock Enable

ValueDescription
0The APBB clock for the DSU is stopped
1The APBB clock for the DSU is enabled

Bit 0 – USB USB APBB Clock Enable

ValueDescription
0The APBB clock for the USB is stopped
1The APBB clock for the USB is enabled