13.6.8.10 APBB Mask
| Name: | APBBMASK |
| Offset: | 0x18 |
| Reset: | 0x00000017 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Reserved[28:21] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Reserved[20:13] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Reserved[12:5] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved[4:0] | NVMCTRL | DSU | USB | ||||||
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | |
Bits 31:3 – Reserved[28:0] Reserved bits
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0.
Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the NVMCTRL is stopped |
| 1 | The APBB clock for the NVMCTRL is enabled |
Bit 1 – DSU DSU APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the DSU is stopped |
| 1 | The APBB clock for the DSU is enabled |
Bit 0 – USB USB APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the USB is stopped |
| 1 | The APBB clock for the USB is enabled |