13.6.8.9 APBA Mask

Name: APBAMASK
Offset: 0x14
Reset: 0x00001FFF
Property: PAC Write-Protection

Bit 3130292827262524 
 Reserved[19:12] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 Reserved[11:4] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 Reserved[3:0] PORTEICRTC 
Access RRRRRRR 
Reset 0001111 
Bit 76543210 
 WDTGCLKSUPCOSC32KCTRLOSCCTRLRSTCMCLKPM 
Access RR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 31:12 – Reserved[19:0] For future use

Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0.

Bit 10 – PORT PORT APBA Clock Enable

ValueDescription
0 The APBA clock for the PORT is stopped.
1 The APBA clock for the PORT is enabled.

Bit 9 – EIC EIC APBA Clock Enable

ValueDescription
0 The APBA clock for the EIC is stopped.
1 The APBA clock for the EIC is enabled.

Bit 8 – RTC RTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RTC is stopped.
1 The APBA clock for the RTC is enabled.

Bit 7 – WDT WDT APBA Clock Enable

ValueDescription
0 The APBA clock for the WDT is stopped.
1 The APBA clock for the WDT is enabled.

Bit 6 – GCLK GCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the GCLK is stopped.
1 The APBA clock for the GCLK is enabled.

Bit 5 – SUPC SUPC APBA Clock Enable

ValueDescription
0 The APBA clock for the SUPC is stopped.
1 The APBA clock for the SUPC is enabled.

Bit 4 – OSC32KCTRL OSC32KCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSC32KCTRL is stopped.
1 The APBA clock for the OSC32KCTRL is enabled.

Bit 3 – OSCCTRL OSCCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSCCTRL is stopped.
1 The APBA clock for the OSCCTRL is enabled.

Bit 2 – RSTC RSTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RSTC is stopped.
1 The APBA clock for the RSTC is enabled.

Bit 1 – MCLK MCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the MCLK is stopped.
1 The APBA clock for the MCLK is enabled.

Bit 0 – PM PM APBA Clock Enable

ValueDescription
0 The APBA clock for the PM is stopped.
1 The APBA clock for the PM is enabled.