These bits define the division ratio of the main
clock prescaler (2n) related to the
Backup clock domain. To ensure correct operation, frequencies must be selected so
that FCPU
≥ FLP
≥ F_BUP (i.e. BUPDIV ≥
LPDIV ≥ CPUDIV). Also, frequencies must never exceed the specified maximum
frequency for each clock domain.
Value | Name | Description |
---|
0x01 |
DIV1 |
Divide by 1 |
0x02 |
DIV2 |
Divide by 2 |
0x04 |
DIV4 |
Divide by 4 |
0x08 |
DIV8 |
Divide by 8 |
0x10 |
DIV16 |
Divide by 16 |
0x20 |
DIV32 |
Divide by 32 |
0x40 |
DIV64 |
Divide by 64 |
0x80 |
DIV128 |
Divide by 128 |
others |
- |
Reserved |