13.8.6.4.4 Regulator Automatic Low Power Mode
In standby mode, the PM selects either the main or the low power voltage regulator to supply the VDDCORE. If all power domains are in retention state, the low power voltage regulator is used.
If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details.
| Sleep Modes |
STDBYCFG. VREGSMOD |
SleepWalking(1) | Regulator state for VDDCORE |
|---|---|---|---|
| Active | - | - | main voltage regulator |
| Idle | - | - | main voltage regulator |
| Standby (at least one PD is active) | 0x0: AUTO | NO | low power regulator |
| YES | main voltage regulator | ||
| 0x1: PERFORMANCE | - | main voltage regulator | |
| 0x2: LP(2) | -(2) | low power regulator | |
| Standby (all PD inretention) | - | - | low power regulator |
Note:
- SleepWalking is running on GCLK clock or synchronous clock. This is not related to OSC32K, XOSC32K or OSCULP32K clocks.
- Must only be used when SleepWalking is running on GCLK with 32KHz source.