13.8.6.4.6 Wake-Up Time

As shown in the figure below, total wake-up time depends on:

• Latency due to Power Domain Gating:

  Usually, wake-up time is measured with the assumption that the power domains are already in an active state. When using Power Domain Gating, changing a power domain from a retention to active state will take a certain time; refer to Electrical Characteristics. If all power domains were already in active state in standby sleep mode, this latency is zero. If wake-up time is critical for the application, the power domains can be forced to an active state in standby sleep mode; refer to 13.8.6.4.1 Power Domain Configuration and 13.8.6.4.2 Linked Power Domains for details.

• Latency due to Performance Level and Regulator effect:

  Performance Level has to be taken into account for the global wake-up time. As an example, if PL2 is selected and the device is in standby sleep mode, the voltage level supplied by the ULP voltage regulator is lower than the one used in active mode. When the device wakes up, it takes a certain amount of time for the main regulator to transition to the voltage level corresponding to PL2, causing additional wake-up time.

• Latency due to the CPU clock source wake-up time.
• Latency due to the NVM memory access.