13.8.6.4.3 RAM Automatic Low Power Mode
The RAM is by default put in low power mode (back-biased) if its power domain is in retention state and the device is in standby sleep mode.
This behavior can be changed by configuring the Back Bias bit groups in the Standby Configuration register (STDBYCFG.BBIASxx), refer to the table below for details.
Note: in standby sleep mode, the DMAC can access the LP
SRAM only when the power domain PD1 is not in retention and PM.STDBYCFG.BBIASLP=0x0. The
DMAC can access the SRAM in standby sleep mode only when the power domain PD2 is not in
retention and PM.STDBYCFG.BBIASHS=0x0.
| STBYCDFG.BBIASxx config | RAM | |
|---|---|---|
| 0x0 | Retention Back Biasing mode | RAM is back-biased if its power domain is in retention state |
| 0x1 | Standby Back Biasing mode | RAM is back-biased if the device is in standby sleep mode |
| 0x2 | Standby OFF mode | RAM is OFF if the device is in standby sleep mode |
| 0x3 | Always OFF mode | RAM is OFF if its power domain is in retention state |