13.9.8.8 DFLL48M Value

Name: DFLLVAL
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection, Read-Synchronized using DFLLSYNC.READREQ, Write-Synchronized using STATUS.DFLLRDY=1

Bit 3130292827262524 
 DIFF[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DIFF[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 COARSE[5:0]FINE[9:8] 
Access RRRRRRR/WR/W 
Reset 00000000 
Bit 76543210 
 FINE[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:16 – DIFF[15:0] Multiplication Ratio Difference

In closed-loop mode (DFLLCTRL.MODE=1), this bit group indicates the difference between the ideal number of DFLL cycles and the counted number of cycles. In open-loop mode, this value is not updated and hence, invalid.

Bits 15:10 – COARSE[5:0] Coarse Value

Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.

Bits 9:0 – FINE[9:0] Fine Value

Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.