13.9.8.16 DPLL Status

Name: DPLLSTATUS
Offset: 0x3C
Reset: 0x00
Property: 

Bit 76543210 
       CLKRDYLOCK 
Access RR 
Reset 00 

Bit 1 – CLKRDY Output Clock Ready

ValueDescription
0 The DPLL output clock is off.
1 The DPLL output clock in on.

Bit 0 – LOCK DPLL Lock status bit

ValueDescription
0 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the target frequency.
1 The DPLL Lock signal is asserted when the desired frequency is reached.