34.20.4 SMC Mode Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.
Name: | SMC_MODEx |
Offset: | 0x0C + x*0x10 [x=0..5] |
Reset: | 0x10001000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PS[1:0] | PMEN | ||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 1 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TDF_MODE | TDF_CYCLES[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DBW[1:0] | BAT | ||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 1 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EXNW_MODE[1:0] | WRITE_MODE | READ_MODE | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 29:28 – PS[1:0] Page Size
If Page mode is enabled, this field indicates the size of the page in bytes.
Value | Name | Description |
---|---|---|
0 | BYTE_4 | 4-byte page |
1 | BYTE_8 | 8-byte page |
2 | BYTE_16 | 16-byte page |
3 | BYTE_32 | 32-byte page |
Bit 24 – PMEN Page Mode Enabled
Value | Description |
---|---|
1 | Asynchronous burst read in Page mode is applied on the corresponding chip select. |
0 | Standard read is applied. |
Bit 20 – TDF_MODE TDF Optimization
Value | Description |
---|---|
1 | TDF optimization enabled—The number of TDF Wait states is optimized using the setup period of the next read/write access. |
0 | TDF optimization disabled—The number of TDF Wait states is inserted before the next access begins. |
Bits 19:16 – TDF_CYCLES[3:0] Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provides one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.
Bits 13:12 – DBW[1:0] Data Bus Width
Value | Name | Description |
---|---|---|
0 | BIT_8 | 8-bit bus |
1 | BIT_16 | 16-bit bus |
2 | BIT_32 | 32-bit bus |
3 | — | Reserved |
Bit 8 – BAT Byte Access Type
This field is used only if DBW defines a 16 or 32-bit data bus.
Value | Name | Description |
---|---|---|
0 | BYTE_SELECT | Byte select
access type:
|
1 | BYTE_WRITE | Byte write
access type:
|
Bits 5:4 – EXNW_MODE[1:0] NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.
Value | Name | Description |
---|---|---|
0 | DISABLED | Disabled Mode—The NWAIT input signal is ignored on the corresponding Chip Select. |
1 | — | Reserved |
2 | FROZEN | Frozen Mode—If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. |
3 | READY | Ready Mode—The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. |
Bit 1 – WRITE_MODE Selection of the Control Signal for Write Operation
Value | Name | Description |
---|---|---|
0 | NCS_CTRL | Write operation controlled by NCS signal—If TDF optimization is enabled (TDF_MODE = 1), TDF Wait states will be inserted after the setup of NCS. |
1 | NWE_CTRL | Write operation controlled by NWE signal—If TDF optimization is enabled (TDF_MODE = 1), TDF Wait states will be inserted after the setup of NWE. |
Bit 0 – READ_MODE Selection of the Control Signal for Read Operation
Value | Name | Description |
---|---|---|
0 | NCS_CTRL | Read
operation controlled by NCS signal
|
1 | NRD_CTRL | Read
operation controlled by NRD signal
|