34.20.7 SMC Off-Chip Memory Scrambling Key2
Register
This register is a ‘Write-once’ register: the first write access after a system
reset prevents any further modification of the register value.
This register is erased if a tamper is detected on fast wakeup pins and bit
SMC_OCMS.TAMPCLR = 1.
Name: | SMC_KEY2 |
Offset: | 0x88 |
Reset: | 0x00000000 |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY2[31:24] | |
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY2[23:16] | |
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| KEY2[15:8] | |
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| KEY2[7:0] | |
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – KEY2[31:0] Off-Chip Memory Scrambling (OCMS) Key Part
2
When off-chip memory
scrambling is enabled, KEY1 and KEY2 values determine data
scrambling.