34.20 Register Summary

The SMC is programmed using the registers listed below. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. The number of SMC_SETUP, SMC_PULSE, SMC_CYCLE and SMC_MODE registers depends on the number of chip selects. Sixteen bytes (0x10) are required per chip select.

Note: The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	SMC_SETUP0	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x04	SMC_PULSE0	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x08	SMC_CYCLE0	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x0C	SMC_MODE0	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x10	SMC_SETUP1	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x14	SMC_PULSE1	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x18	SMC_CYCLE1	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x1C	SMC_MODE1	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x20	SMC_SETUP2	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x24	SMC_PULSE2	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x28	SMC_CYCLE2	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x2C	SMC_MODE2	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x30	SMC_SETUP3	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x34	SMC_PULSE3	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x38	SMC_CYCLE3	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x3C	SMC_MODE3	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x40	SMC_SETUP4	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x44	SMC_PULSE4	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x48	SMC_CYCLE4	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x4C	SMC_MODE4	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x50	SMC_SETUP5	31:24			NCS_RD_SETUP[5:0]
		23:16			NRD_SETUP[5:0]
		15:8			NCS_WR_SETUP[5:0]
		7:0			NWE_SETUP[5:0]
0x54	SMC_PULSE5	31:24		NCS_RD_PULSE[6:0]
		23:16		NRD_PULSE[6:0]
		15:8		NCS_WR_PULSE[6:0]
		7:0		NWE_PULSE[6:0]
0x58	SMC_CYCLE5	31:24								NRD_CYCLE[8]
		23:16	NRD_CYCLE[7:0]
		15:8								NWE_CYCLE[8]
		7:0	NWE_CYCLE[7:0]
0x5C	SMC_MODE5	31:24			PS[1:0]					PMEN
		23:16				TDF_MODE	TDF_CYCLES[3:0]
		15:8			DBW[1:0]					BAT
		7:0			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
0x60 ... 0x7F	Reserved
0x80	SMC_OCMS	31:24
		23:16
		15:8			CS5SE	CS4SE	CS3SE	CS2SE	CS1SE	CS0SE
		7:0				TAMPCLR				SMSE
0x84	SMC_KEY1	31:24	KEY1[31:24]
		23:16	KEY1[23:16]
		15:8	KEY1[15:8]
		7:0	KEY1[7:0]
0x88	SMC_KEY2	31:24	KEY2[31:24]
		23:16	KEY2[23:16]
		15:8	KEY2[15:8]
		7:0	KEY2[7:0]
0x8C ... 0x8F	Reserved
0x90	SMC_SRIER	31:24
		23:16
		15:8
		7:0								SRIE
0x94 ... 0xE3	Reserved
0xE4	SMC_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0								WPEN
0xE8	SMC_WPSR	31:24							SWETYP[1:0]
		23:16	WPVSRC[15:8]
		15:8	WPVSRC[7:0]
		7:0					SWE	SEQE		WPVS