55.5.3 TDES Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the TDES Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name:	TDES_IER
Offset:	0x10
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
								SECE
Access								W
Reset								–


Bit	15	14	13	12	11	10	9	8
								URAD
Access								W
Reset								–


Bit	7	6	5	4	3	2	1	0
								DATRDY
Access								W
Reset								–

Bit 16 – SECE Security and/or Safety Event Interrupt Enable

Bit 8 – URAD Unspecified Register Access Detection Interrupt Enable

Bit 0 – DATRDY Data Ready Interrupt Enable

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.