55.5.6 TDES Interrupt Status Register
| Name: | TDES_ISR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SECE | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| URAT[1:0] | URAD | ||||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATRDY | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 16 – SECE Security and/or Safety Event Interrupt Mask
| Value | Description |
|---|---|
| 0 | There is no security report in TDES_WPSR. |
| 1 | One security flag is set in TDES_WPSR. |
Bits 13:12 – URAT[1:0] Unspecified Register Access (cleared by setting bit TDES_CR.SWRST)
Only the last Unspecified Register Access Type is available through the URAT field.
| Value | Name | Description |
|---|---|---|
| 0 | IDR_WR_PROCESSING | TDES_IDATAR written during data processing when SMOD = 0x2 mode. |
| 1 | ODR_RD_PROCESSING | TDES_ODATAR read during data processing. |
| 2 | MR_WR_PROCESSING | TDES_MR written during data processing. |
| 3 | WOR_RD_ACCESS | Write-only register read access. |
Bit 8 – URAD Unspecified Register Access Detection Status (cleared by setting TDES_CR.SWRST)
| Value | Description |
|---|---|
| 0 | No unspecified register access has been detected since the last write of TDES_CR.SWRST. |
| 1 | At least one unspecified register access has been detected since the last write of TDES_CR.SWRST. |
Bit 0 – DATRDY Data Ready (cleared by setting TDES_CR.START or TDES_CR.SWRST, or by reading TDES_ODATARx)
If TDES_MR.LOD = 1: In Manual and Auto modes, the DATRDY flag can also be cleared by writing at least one TDES_IDATARx.
| Value | Description |
|---|---|
| 0 | Output data is not valid. |
| 1 | Encryption or decryption process is completed. |