55.5.15 TDES Write Protection Status Register
Name: | TDES_WPSR |
Offset: | 0xE8 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
ECLASS | SWETYP[3:0] | ||||||||
Access | R | R | R | R | R | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
WPVSRC[15:8] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
WPVSRC[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PKRPVS | SWE | SEQE | CGD | WPVS | |||||
Access | R | R | R | R | R | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 31 – ECLASS Software Error Class (cleared on read)
Value | Name | Description |
---|---|---|
0 | WARNING | An abnormal access that does not affect system functionality. |
1 | ERROR | An access is performed into key, input data, control registers while the TDES is performing an encryption/decryption or a start is request by software or DMA while the key is not fully configured. |
Bits 27:24 – SWETYP[3:0] Software Error Type (cleared on read)
Value | Name | Description |
---|---|---|
0 | READ_WO | A write-only register has been read (Warning). |
1 | WRITE_RO | TDES is enabled and a write access has been performed on a read-only register (Warning). |
2 | UNDEF_RW | Access to an undefined address (Warning). |
3 | CTRL_START | Abnormal use of TDES_CR.START command when DMA access is configured. |
4 | WEIRD_ACTION | A key write, init value write, output data read, Mode register write, Private Key bus access or XTEA round register has been performed while a current processing is in progress (abnormal). |
5 | INCOMPLETE_KEY | A tentative of start is required while the keys are not fully loaded into TDES_KEYxWRy. |
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source (cleared on read)
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1, WPVSRC returns the address of the write-protected violation.
Bit 4 – PKRPVS Private Key Register Protection Violation Status (cleared on read)
Value | Description |
---|---|
0 | No Private Key internal register access violation has occurred since the last read of TDES_WPSR. |
1 | A Private Key internal register access violation has occurred since the last read of TDES_WPSR. |
Bit 3 – SWE Software Control Error (cleared on read)
Value | Description |
---|---|
0 | No software error has occurred since the last read of TDES_WPSR. |
1 | A software error has occurred since the last read of TDES_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0). |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value | Description |
---|---|
0 | No peripheral internal sequencer error has occurred since the last read of TDES_WPSR. |
1 | A peripheral internal sequencer error has occurred since the last read of TDES_WPSR. This flag is set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value | Description |
---|---|
0 | The clock monitoring circuitry has not been corrupted since the last read of TDES_WPSR. Under normal operating conditions, this bit is always cleared. |
1 | The clock monitoring circuitry has been corrupted since the last read of TDES_WPSR. This flag is set in case of abnormal clock signal waveform (glitch). |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
Value | Description |
---|---|
0 | No write protection violation has occurred since the last read of TDES_WPSR. |
1 | A write protection violation has occurred since the last read of TDES_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. |