12.1.4.7.1 NAND Flash Boot: NAND Flash Detection

After the NAND Flash interface configuration, a reset command is sent to the memory.

The reset time of the NAND memory, after this reset command, must not be higher than 100 µs.

Hardware ECC detection and correction are provided by the PMECC peripheral. See Programmable Multibit Error Correction Code Controller (PMECC) for more details.

The Boot Program is able to retrieve NAND Flash parameters and ECC requirements using either one of the following methods:

It is highly recommended to use Method 1, since it indicates exactly how the PMECC has been configured to read or write the bootable program in the NAND Flash, and does not rely only on the NAND Flash capabilities.

Once the Boot program retrieves the parameter, using one of the above two methods, it reads the first page again, with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM.

Note: Booting on 16-bit NAND Flash is not possible; only 8-bit NAND Flash memories are supported.
Figure 12-7. Boot NAND Flash Download