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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
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12
Boot Strategies
12.1
Standard Boot Strategy
12.1.4
Boot Configuration
12.1.4.7
Detailed Memory Boot Procedures
Introduction
Features
Reference Document
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Memories
8
System Controller
9
Peripherals
10
ARM926EJ-S Processor
11
Debug and Test
12
Boot Strategies
12.1
Standard Boot Strategy
12.1.1
Description
12.1.2
Flow Diagram
12.1.3
Chip Setup
12.1.4
Boot Configuration
12.1.4.1
Default Boot Sequence (Without Boot Configuration Packet)
12.1.4.2
Using Boot Configuration Packet
12.1.4.3
Boot Sequence Controller Configuration Register
Boot Sequence Controller Configuration Register
12.1.4.4
Boot Configuration User Interface
12.1.4.5
NVM Boot Sequence
12.1.4.6
Valid Bootstrap Code Detection
12.1.4.7
Detailed Memory Boot Procedures
12.1.4.7.1
NAND Flash Boot: NAND Flash Detection
12.1.4.7.2
NAND Flash Boot: PMECC Error Detection and Correction
12.1.4.7.3
SD Card/e.MMC Boot
12.1.4.7.4
SPI Flash Boot
12.1.4.7.5
QSPI NOR Flash Boot
12.1.4.8
Hardware and Software Constraints
12.1.5
SAM-BA Monitor
12.2
Secure Boot Strategy
13
System Controller Write Protection (SYSCWP)
14
General Purpose Backup Registers (GPBR)
15
Watchdog Timer (WDT)
16
Reset Controller (RSTC)
17
Real-Time Timer (RTT)
18
Real-Time Clock (RTC)
19
Shutdown Controller (SHDWC)
20
Periodic Interval Timer (PIT)
21
64-bit Periodic Interval Timer (PIT64B)
22
Debug Unit (DBGU)
23
OTP Memory Controller (OTPC)
24
Special Function Registers (SFR)
25
Bus Matrix (MATRIX)
26
Advanced Interrupt Controller (AIC)
27
Slow Clock Controller (SCKC)
28
Clock Generator
29
Power Management Controller (PMC)
30
Parallel Input/Output Controller (PIO)
31
External Bus Interface (EBI)
32
DDR-SDRAM Controller (MPDDRC)
33
SDRAM Controller (SDRAMC)
34
Static Memory Controller (SMC)
35
Programmable Multibit Error Correction Code Controller (PMECC)
36
Programmable Multibit ECC Error Location Controller (PMERRLOC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
2D Graphics Engine (GFX2D)
40
Ethernet MAC 10/100 (EMAC)
41
USB Device High Speed Port (UDPHS)
42
USB Host High Speed Port (UHPHS)
43
Audio Class D Amplifier (CLASSD)
44
Inter-IC Sound Multi-Channel Controller (I2SMCC)
45
Synchronous Serial Controller (SSC)
46
Flexible Serial Communication Controller (FLEXCOM)
47
Quad Serial Peripheral Interface (QSPI)
48
Secure Digital MultiMedia Card Controller (SDMMC)
49
Image Sensor Interface (ISI)
50
Controller Area Network (CAN)
51
Timer Counter (TC)
52
Pulse Width Modulation Controller (PWM)
53
Advanced Encryption Standard (AES)
54
Secure Hash Algorithm (SHA)
55
Triple Data Encryption Standard (TDES)
56
Random Number Generator (TRNG)
57
Analog-to-Digital Controller (ADC)
58
Electrical Characteristics
59
Mechanical Characteristics
60
Marking
61
Ordering Information
62
Revision History
Microchip Information
12.1.4.7 Detailed Memory Boot Procedures
