33.6.8 Interface with Multiplexed Data/Address Lines and Data/Address/Command Lines

This feature takes advantage of the SDRAM protocol to reduce the pin count by multiplexing address and data lines or address, data and command lines. Up to 16 lines can be reduced depending on the configuration of the SDRAM.

Using this feature reduces the efficiency of the SDRAM by adding one clock cycle during write access.

When address, data and command lines are multiplexed, as SDA10 is multiplexed, refresh operations increase the latency. It is not possible to perform an access to another device during auto-refresh process.

Figure 33-9. Multiplexed Address/Data, Connection to 1x16 SDRAM Interface
Figure 33-10. Multiplexed Address/Data/Command, Connection to 1x16 SDRAM Interface
Table 33-8. 16-Mbit SDR-SDRAM, 512 Kbits*16 bits*2 Banks: Multiplexed Address/Data
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE––––BKA10A9A8A7A6A5A4A3A2A1A0
Table 33-9. 16-Mbit SDR-SDRAM, 512 Kbits*16 bits*2 Banks: Multiplexed Address/Data/Command
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0]RASCASWE–BKA10A9A8A7A6A5A4A3A2A1A0
Table 33-10. 64-Mbit SDR-SDRAM, 1 Mbit*16 bits*4 Banks, 128-Mbit SDR-SDRAM, 2 Mbits*16 bits*4 Banks: Multiplexed Address/Data
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE––BKBKA11A10A9A8A7A6A5A4A3A2A1A0
Table 33-11. 64-Mbit SDR-SDRAM, 1 Mbit*16 bits*4 Banks, 128-Mbit SDR-SDRAM, 2 Mbits*16 bits*4 Banks: Multiplexed Address/Data/ Command
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0], RASCASWEBKBKA11A10A9A8A7A6A5A4A3A2A1A0
Table 33-12. 256-Mbit SDR-SDRAM, 4 Mbits*16 bits*4 Banks: Multiplexed Address/Data
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE–BKBKA12A11A10A9A8A7A6A5A4A3A2A1A0
Table 33-13. 256-Mbit SDR-SDRAM, 4 Mbits*16 bits*4 Banks: Multiplexed Address/Data/Command
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK, CKE, SDCS, DM[1:0], RAS, CASWEBKBKA12A11A10A9A8A7A6A5A4A3A2A1A0