33.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	SDRAMC_MR	31:24
		23:16
		15:8
		7:0						MODE[2:0]
0x04	SDRAMC_TR	31:24
		23:16
		15:8					COUNT[11:8]
		7:0	COUNT[7:0]
0x08	SDRAMC_CR	31:24	TXSR[3:0]				TRAS[3:0]
		23:16	TRCD[3:0]				TRP[3:0]
		15:8	TRC_TRFC[3:0]				TWR[3:0]
		7:0	DBW	CAS[1:0]		NB	NR[1:0]		NC[1:0]
0x0C ... 0x0F	Reserved
0x10	SDRAMC_LPR	31:24
		23:16								SELFDONE
		15:8		SELFAUTO	TIMEOUT[1:0]		DS[1:0]		TCSR[1:0]
		7:0		PASR[2:0]					LPCB[1:0]
0x14	SDRAMC_IER	31:24
		23:16
		15:8
		7:0							SECE	RES
0x18	SDRAMC_IDR	31:24
		23:16
		15:8
		7:0							SECE	RES
0x1C	SDRAMC_IMR	31:24
		23:16
		15:8
		7:0							SECE	RES
0x20	SDRAMC_ISR	31:24
		23:16
		15:8
		7:0							SECE	RES
0x24	SDRAMC_MDR	31:24
		23:16
		15:8
		7:0			SHIFT_SAMPLING[1:0]				MD[1:0]
0x28	SDRAMC_CFR1	31:24
		23:16
		15:8					CMD_MUX	ADD_DATA_MUX		UNAL
		7:0					TMRD[3:0]
0x2C	SDRAMC_OCMS	31:24
		23:16
		15:8
		7:0				TAMPCLR				SDR_SE
0x30	SDRAMC_OCMS_KEY1	31:24	KEY1[31:24]
		23:16	KEY1[23:16]
		15:8	KEY1[15:8]
		7:0	KEY1[7:0]
0x34	SDRAMC_OCMS_KEY2	31:24	KEY2[31:24]
		23:16	KEY2[23:16]
		15:8	KEY2[15:8]
		7:0	KEY2[7:0]
0x38 ... 0x3B	Reserved
0x3C	SDRAMC_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0							WPITEN	WPEN
0x40	SDRAMC_WPSR	31:24	ECLASS					SWETYP[2:0]
		23:16
		15:8	WPVSRC[7:0]
		7:0					SWE	SEQE	CGD	WPEN