33.6.9 Register Write Protection

To prevent any single software error from corrupting SDRAMC behavior, some registers in the address space can be write-protected by setting the WPEN and WPITEN bits in the SDRAMC Write Protection Mode Register (SDRAMC_WPMR).

If a write access to a write-protected register is detected, the WPVS flag in the SDRAMC Write Protection Status Register (SDRAMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading the SDRAMC_WPSR.

The following registers can be write-protected:

• SDRAMC Mode Register
• SDRAMC Refresh Timer Register
• SDRAMC Configuration Register
• SDRAMC Memory Device Register
• SDRAMC Configuration Register 1
• SDRAMC OCMS Register
• SDRAMC OCMS KEY1 Register
• SDRAMC OCMS KEY2 Register