33.6.10 Security and Safety Analysis and Reports

Several types of checks are performed when the SDRAMC is accessing the memory device.

The peripheral clock of the SDRAMC is monitored by specific circuitry to detect abnormal waveforms on the internal clock net that may affect the behavior of the SDRAMC. Corruption on the triggering edge of the clock or a pulse with a minimum duration may be identified. If the flag SDRAMC_WPSR.CGD is set, an abnormal condition occurred on the peripheral clock. This flag is not set under normal operating conditions.

The internal sequencer of the SDRAMC is also monitored and if an abnormal state is detected, the flag SDRAMC_WPSR.SEQE is set. This flag is not set under normal operating conditions.

The software accesses to the SDRAMC are monitored and if an incorrect access is performed, the flag SDRAMC_WPSR.SWE is set. The type of incorrect/abnormal software access is reported in the SDRAMC_WPSR.SWETYP field (see SDRAMC_WPSR for details) , e.g. , writing a new configuration (SDRAMC_CR, SDRAMC_CFR1, SDRAMC_HSR, SDRAMC_OCMS, SDRAMC_KEY1/2) after the initializat ion of the SDRAMC ( i .e. , i f SDRAMC_TR.COUNT > 0) i s an er ror . SDRAMC_WPSR.ECLASS is an indicator reporting the criticality of the SWETYP report.

The flags CGD, SEQE, SWE and WPVS are automatically cleared when SDRAMC_WPSR is read.

If one of these flags is set, the flag SDRAMC_ISR.SECE is set and can trigger an interrupt if the SDRAMC_IMR.SECE bit is ‘1’. SECE is cleared by reading SDRAMC_ISR.