15.5.1 Watchdog Timer Control Register
The WDT_CR register values must not be modified within three slow clock periods following a restart of the WDT performed by a write access in WDT_CR. Any modification will cause the WDT to trigger an end of period earlier than expected.
| Name: | WDT_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LOCKMR | WDRSTT | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
Bits 31:24 – KEY[7:0] Password
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 4 – LOCKMR Lock Mode Register Write Access
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Locks the configuration registers if KEY is written to 0xA5. Write accesses to WDT_MR, WDT_WLR and WDT_ILR have no effect. |
Bit 0 – WDRSTT Watchdog Restart
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Restarts the WDT if KEY is written to 0xA5. |