15.5.3 Watchdog Timer Value Register
| Name: | WDT_VR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNTER[11:8] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COUNTER[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 11:0 – COUNTER[11:0] Watchdog Down Counter Value
Shows the current value of the WDT down counter for debug operation.
Due to the asynchronous operation of the WDT with respect to the rest of the chip, to be certain that the value read in this register is valid and stable, it is necessary to read the register twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.