15.5.4 Watchdog Timer Window Level Register
Name: | WDT_WLR |
Offset: | 0x0C |
Reset: | 0x00000FFF |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
RPTH[11:8] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RPTH[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PERIOD[11:8] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 1 | 1 | 1 | 1 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PERIOD[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bits 27:16 – RPTH[11:0] Repeat Threshold
Defines the period before which a WDT restart generates an interrupt.
Bits 11:0 – PERIOD[11:0] Watchdog Period
Defines the period after which the WDT generates a reset.