35.6.12 PMECC ECC x Register
Note: The block of registers PMECC_ECCx[x=0..10] is instanced 8 times in the user
interface.
| Name: | PMECC_ECCx |
| Offset: | 0x40 + x*0x04 [x=0..10] |
| Reset: | 0xFFFFFFFF |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ECC[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ECC[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ECC[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ECC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 31:0 – ECC[31:0] BCH Redundancy
This register contains the remainder of the division of the codeword by the generator polynomial.