35.6.1 PMECC Configuration Register

Name: PMECC_CFG
Offset: 0x000
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
    AUTO   SPAREEN 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
    NANDWR  PAGESIZE[1:0] 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
    SECTORSZ BCH_ERR[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 20 – AUTO Automatic Mode Enable

This bit is only relevant in NAND Read Mode, when spare enable is activated.

ValueDescription
0

Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address).

1

Indicates that the spare is error protected. In this case, the ECC computation takes into account the whole spare area minus the ECC area in the ECC computation operation.

Bit 16 – SPAREEN Spare Enable

  • For NAND write access:

    — 0: The spare area is skipped

    — 1: The spare area is protected with the last sector of data.

  • For NAND read access:

    — 0: The spare area is skipped.

    — 1: The spare area contains protected data or only redundancy information.

Bit 12 – NANDWR NAND Write Access

ValueDescription
0

NAND read access

1

NAND write access

Bits 9:8 – PAGESIZE[1:0] Number of Sectors in the Page

ValueNameDescription
0 PAGESIZE_1SEC

1 sector for main area (512 or 1024 bytes)

1 PAGESIZE_2SEC

2 sectors for main area (1024 or 2048 bytes)

2 PAGESIZE_4SEC

4 sectors for main area (2048 or 4096 bytes)

3 PAGESIZE_8SEC

8 errors for main area (4096 or 8192 bytes)

Bit 4 – SECTORSZ Sector Size

ValueDescription
0

The ECC computation is based on a sector of 512 bytes.

1

The ECC computation is based on a sector of 1024 bytes.

Bits 2:0 – BCH_ERR[2:0] Error Correct Capability

ValueNameDescription
0 BCH_ERR2

2 errors

1 BCH_ERR4

4 errors

2 BCH_ERR8

8 errors

3 BCH_ERR12

12 errors

4 BCH_ERR24

24 errors