40.7.17 Waveform

Note: This register is write-synchronized: SYNCBUSY.WAVE must be checked to ensure the WAVE register bits synchronization is complete.

Name:	WAVE
Offset:	0x3C
Reset:	0x00000000
Property:	Enable-Protected Bits, Write-Synchronized Bits


Bit	31	30	29	28	27	26	25	24
					SWAP3	SWAP2	SWAP1	SWAP0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
					POL3	POL2	POL1	POL0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
					CICCEN3	CICCEN2	CICCEN1	CICCEN0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CIPEREN	RAMP[2:0]				WAVEGEN[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x

Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not affect the swap operation.

Note: This bit is not enable-protected. This bit is write-synchronized.

Bits 16, 17, 18, 19 – POL Channel Polarity x

Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.

Note: This bit field is not enable-protected. This bit field is write-synchronized.

Value	Name	Description
0	SINGLESLOPEPOL0	Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value (single-slope PWM waveform generation).
1	SINGLESLOPEPOL1	Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value (single-slope PWM waveform generation).
0	DUALSLOPEPOL0	Compare output is set to ~DIR when TCC counter matches CCx value (dual-slope PWM waveform generation).
1	DUALSLOPEPOL1	Compare output is set to DIR when TCC counter matches CCx value (dual-slope PWM waveform generation).
0	DUALCOMPAREPOL0	Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCx value and set to ~DIR when TCC counter matches CC[x+WO_NUM/2] value (dual compare PWM waveform generation).
1	DUALCOMPAREPOL1	Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCx value and set to DIR when TCC counter matches CC[x+WO_NUM/2] value (dual compare PWM waveform generation).

Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x

Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is copied-back into the CCx register on UPDATE condition.

Note: This bit is not enable-protected. This bit is write-synchronized.

Bit 7 – CIPEREN Circular Period Enable

Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back into the PERB register on UPDATE condition.

Note: This bit is not enable-protected. This bit is write-synchronized.

Bits 6:4 – RAMP[2:0] Ramp Operation

These bits select Ramp operation (RAMP).

Note: This bit field is enable-protected. This bit field is not write-synchronized.

Value	Name	Description
0x0	RAMP1	RAMP1 operation
0x1	RAMP2A	Alternative RAMP2 operation
0x2	RAMP2	RAMP2 operation
0x3	RAMP2C	Critical RAMP2 operation
0x4	RAMP2CS	Critical Swapped RAMP2 operation

Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation

These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation should be used.

Note: This bit field is enable-protected. This bit field is not write-synchronized.


Value	Name	Description
		Operation	Top	Update	Waveform Output On Match	Waveform Output On Update	OVFIF/Event Up Down
0x0	NFRQ	Normal Frequency	PER	TOP/Zero	Toggle	Stable	TOP	Zero
0x1	MFRQ	Match Frequency	CC0	TOP/Zero	Toggle	Stable	TOP	Zero
0x2	NPWM	Normal PWM	PER	TOP/Zero	Set	Clear	TOP	Zero
0x3	DPWM	Dual Compare PWM	PER	TOP/ZERO	Set/Clear	Clear	TOP	Zero
0x4	DSCRITICAL	Dual-slope PWM	PER	Zero	~DIR	Stable	–	Zero
0x5	DSBOTTOM	Dual-slope PWM	PER	Zero	~DIR	Stable	–	Zero
0x6	DSBOTH	Dual-slope PWM	PER	TOP & Zero	~DIR	Stable	TOP	Zero
0x7	DSTOP	Dual-slope PWM	PER	Zero	~DIR	Stable	TOP	–