10.1.2 Data Flash
The PIC32CM LE00/LS00/LS60 family of devices embed up to 16 KB of internal Data Flash with Write-While-Read (WWR) capability mapped at address 0x0040 0000.
The Data Flash can be programmed or erased while reading the Flash memory. It is not possible
to read the Data Flash while writing or erasing the Flash.
Note: The Data Flash memory can be
executable, but requires more cycles to be read which may affect system
performance.
The Data Flash cannot be cached.
The Data Flash is organized into rows, where each row contains four pages.
The Data Flash has a row-erase and a page-write granularity.
CAUTION: For this Flash technology, a maximum number of 8 consecutive writes is
allowed per row. Once this number is reached, a row erase is mandatory.
| Device | Memory Size [KB] | Number of Rows | Row size [Bytes] | Number of Pages | Page size [Bytes] |
|---|---|---|---|---|---|
| PIC32CM5164 | 16 | 64 | 256 | 256 | 64 |
| PIC32CM2532 (LE00/LS00 only) | 8 | 32 | 128 | ||
| PIC32CM1216 (LE00/LS00 only) | 4 | 16 | 64 |
The Data Flash is divided into one or two regions.
Each region has a dedicated lock bit preventing from writing and erasing pages on it.
| Device | PIC32CM LE00 | PIC32CM LS00/LS60 |
|---|---|---|
| Number of Data FLASH Lock Regions | 1 | 2 |
| Regions Name | Data Flash | Secure Data Flash/Non-Secure Data Flash |
Note:
- Refer to the NVM Memory Organization figures in the chapter “NVMCTRL” to obtain the definitions of the different regions definition.
- The regions size is configured by the Boot ROM at device start-up by reading the NVM Boot Configuration Row (BOCOR). Refer to the chapter Boot ROM for additional information.