10.1.1 Flash
The PIC32CM LE00/LS00/LS60 family of devices embed up to 512 KB of internal Flash mapped at address 0x00000000. The Flash has a 512-byte (64 lines of 8 bytes) direct-mapped cache which is enabled by default after power-up. The Flash is organized into rows, where each row contains four pages. The Flash has a row-erase and a page-write granularity.
CAUTION: For this Flash technology, a maximum number of eight consecutive writes
is allowed per row. Once this number is reached, a row erase is mandatory.
| Device | Memory Size [KB] | Number of Rows | Row size [Bytes] | Number of Pages | Page size [Bytes] |
|---|---|---|---|---|---|
| PIC32CM5164 | 512 | 2048 | 256 | 8192 | 64 |
| PIC32CM2532 (LE00/LS00 only) | 256 | 1024 | 4096 | ||
| PI32CM1216 (LE00/LS00 only) | 128 | 512 | 2048 |
The Flash is divided in different regions and each region has a dedicated lock bit preventing from writing and erasing pages on it.
| Device | PIC32CM LE00 | PIC32CM LS00/LS60 |
|---|---|---|
| Number of Flash Lock Regions | 2 | 3 |
| Regions Name |
Flash (BOOT region) /Flash (APPLICATION region) |
Secure + NSC Flash (BOOT region) Secure + NSC Flash (APPLICATION region) Non-Secure Flash (APPLICATION region) |
Note:
- Refer to the NVM Memory Organization figures in the “NVMCTRL” chapter to get the different regions definition.
- The regions size is configured by the Boot ROM at device start-up by reading the NVM Boot Configuration Row (BOCOR). Refer to the Boot ROM chapter for more information.