34.7.2 Control B


Bit	31	30	29	28	27	26	25	24
							LINCMD[1:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	FIFOCLR[1:0]						RXEN	TXEN
Access	R/W	R/W					R/W	R/W
Reset	0	0					0	0


Bit	15	14	13	12	11	10	9	8
			PMODE			ENC	SFDE	COLDEN
Access			R/W			R/W	R/W	R/W
Reset			0			0	0	0


Bit	7	6	5	4	3	2	1	0
		SBMODE				CHSIZE[2:0]
Access		R/W				R/W	R/W	R/W
Reset		0				0	0	0

Bits 25:24 – LINCMD[1:0] LIN Command

These bits define the LIN header transmission control. This field is only valid in LIN host mode (CTRLA.FORM= LIN Host).

These are strobe bits and will always read back as zero.

Note: This bit field is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.LINCMD synchronization is complete.

Note: This bit field is not enable-protected.

Value	Description
0x0	Normal USART transmission.
0x1	Break field is transmitted when DATA is written.
0x2	Break, sync and identifier are automatically transmitted when DATA is written with the identifier.
0x3	Reserved

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.CTRLB = 0.

Note: This bit field is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.FIFOCLR synchronization is complete.

Note: This bit field is not enable-protected.


Value	Name	Description
0x0	NONE	No action
0x1	TXFIFO	Clear TX FIFO
0x2	RXFIFO	Clear RX FIFO
0x3	BOTH	Clear both TX/RX FIFO

Bit 17 – RXEN Receiver Enable

Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register.

Writing '1' to this bit when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN is cleared and the receiver enable is only effective at the end of the SYNCBUSY.CTRLB synchronization.

Writing '1' to this bit when the USART is enabled requires to wait the end of the SYNCBUSY.CTRLB synchronization to ensure the receiver is enabled.

Note: This bit is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.RXEN synchronization is complete.

Note: This bit is not enable-protected.

Value	Description
0	The receiver is disabled or being enabled.
1	The receiver is enabled or will be enabled when the USART is enabled.

Bit 16 – TXEN Transmitter Enable

Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed.

Writing '1' to this bit when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN is cleared and the transmitter enable is only effective at the end of the SYNCBUSY.CTRLB synchronization.

Writing '1' to this bit when the USART is enabled requires to wait the end of the SYNCBUSY.CTRLB synchronization to ensure the transmitter is enabled.

Note: This bit is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.TXEN synchronization is complete.

Note: This bit is not enable-protected.

Value	Description
0	The transmitter is disabled or being enabled.
1	The transmitter is enabled or will be enabled when the USART is enabled.

Bit 13 – PMODE Parity Mode

This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set.