34.7 Register Summary
Refer to the Registers Description section for more details on register properties and access permissions.
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 | CTRLA | 31:24 | DORD | CPOL | CMODE | FORM[3:0] | ||||
23:16 | SAMPA[1:0] | RXPO[1:0] | TXPO[1:0] | |||||||
15:8 | SAMPR[2:0] | RXINV | TXINV | IBON | ||||||
7:0 | RUNSTDBY | MODE[2:0] | ENABLE | SWRST | ||||||
0x04 | CTRLB | 31:24 | LINCMD[1:0] | |||||||
23:16 | FIFOCLR[1:0] | RXEN | TXEN | |||||||
15:8 | PMODE | ENC | SFDE | COLDEN | ||||||
7:0 | SBMODE | CHSIZE[2:0] | ||||||||
0x08 | CTRLC | 31:24 | TXTRHOLD[1:0] | RXTRHOLD[1:0] | FIFOEN | DATA32B[1:0] | ||||
23:16 | MAXITER[2:0] | DSNACK | INACK | |||||||
15:8 | HDRDLY[1:0] | BRKLEN[1:0] | ||||||||
7:0 | GTIME[2:0] | |||||||||
0x0C | BAUD | 15:8 | BAUD[15:8] | |||||||
7:0 | BAUD[7:0] | |||||||||
0x0E | RXPL | 7:0 | RXPL[7:0] | |||||||
0x0F ... 0x13 | Reserved | |||||||||
0x14 | INTENCLR | 7:0 | ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |
0x15 | Reserved | |||||||||
0x16 | INTENSET | 7:0 | ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |
0x17 | Reserved | |||||||||
0x18 | INTFLAG | 7:0 | ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |
0x19 | Reserved | |||||||||
0x1A | STATUS | 15:8 | ||||||||
7:0 | ITER | TXE | COLL | ISF | CTS | BUFOVF | FERR | PERR | ||
0x1C | SYNCBUSY | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | ||||||||||
7:0 | LENGTH | RXERRCNT | CTRLB | ENABLE | SWRST | |||||
0x20 | RXERRCNT | 7:0 | RXERRCNT[7:0] | |||||||
0x21 | Reserved | |||||||||
0x22 | LENGTH | 15:8 | LENEN[1:0] | |||||||
7:0 | LEN[7:0] | |||||||||
0x24 ... 0x27 | Reserved | |||||||||
0x28 | DATA | 31:24 | DATA[31:24] | |||||||
23:16 | DATA[23:16] | |||||||||
15:8 | DATA[15:8] | |||||||||
7:0 | DATA[7:0] | |||||||||
0x2C ... 0x2F | Reserved | |||||||||
0x30 | DBGCTRL | 7:0 | DBGSTOP | |||||||
0x31 ... 0x33 | Reserved | |||||||||
0x34 | FIFOSPACE | 15:8 | RXSPACE[4:0] | |||||||
7:0 | TXSPACE[4:0] | |||||||||
0x36 | FIFOPTR | 15:8 | CPURDPTR[3:0] | |||||||
7:0 | CPUWRPTR[3:0] |