14.2.4 Secure SRAM Configuration
This register is loaded from UROW during Boot ROM execution.
Important: if BOCOR.SECCFGLOCK
== 0 after exiting the Boot ROM:
- The secure software code of the Flash BOOT region, before passing control on to the secure software code of the Flash APPLICATION region, must lock the IDAU memory security configurations by clearing the IDAU.SECCTRL.SCFGWEN bit.
- Write accesses (W*) are allowed.
| Name: | SCFGR |
| Offset: | 0x0C |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RS[8] | |||||||||
| Access | R/W* | ||||||||
| Reset | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RS[7:0] | |||||||||
| Access | R/W* | R/W* | R/W* | R/W* | R/W* | R/W* | R/W* | R/W* | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 8:0 – RS[8:0] Secure SRAM (RS region) Size
This field defines the size of the Secure (S) SRAM region = RS*0x80 bytes.