25.9.11 Alarm Value in Clock/Calendar mode (CTRLA.MODE=2)
Note: This register is write-synchronized: SYNCBUSY.ALARM0 must be checked to ensure the
ALARM0 register synchronization is complete.
Name: | ALARM0 |
Offset: | 0x20 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Write-Synchronized |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
YEAR[5:0] | MONTH[3:2] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
MONTH[1:0] | DAY[4:0] | HOUR[4] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
HOUR[3:0] | MINUTE[5:2] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MINUTE[1:0] | SECOND[5:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:26 – YEAR[5:0] Year
Bits 25:22 – MONTH[3:0] Month
Bits 21:17 – DAY[4:0] Day
Bits 16:12 – HOUR[4:0] Hour
When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23.
When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1).