18.5.1 Principle of Operation

The GCLK Main (GCLK_MAIN) or the DFLLULP (CLK_DFLLULP) clocks are the sources for the main clock (CLK_MAIN), which in turn is the common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The CLK_MAIN is divided by an 8-bit prescaler. The clock domain (CPU) can be changed on the fly to respond to variable load in the application. Depending on the sleep mode, some clock domains can be turned off.

The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by modules requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the CPU clock (CLK_CPU) and can run even when the CPU clock is turned off in sleep mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on APBx bus, as well as the AHBx clock.