4.2 48-pin VQFN and 48-pin TQFP


48-PIN VQFN and TQFP (Top View)⁽¹⁾⁽²⁾
PIC32CM1216(LE00/LS00)048 PIC32CM2532(LE00/LS00)048 PIC32CM5164(LE00/LS00/LS60)048

Note:

The 48-pin VQFN package is with wettable flanks.
The 48-pin TQFP package is only available for PIC32CM LE00/LS00.

Table 4-2. 48-pin VQFN/48-pin TQFP I/O PINMUX
Pin	Pin Name	A	B^(1,3)						C⁽⁴⁾⁽⁵⁾		D⁽⁴⁾⁽⁵⁾		E⁽²⁾	G	H	I	J⁽²⁾	K		Power Rail	Reset State
VQFN48 / TQFP48	Pin Name	EIC	REF	ADC	AC	PTC	DAC	OPAMP	SERCOM	IOSET	SERCOM ALT	IOSET	TC / TCC	RTC / USB / Debug	AC / GCLK	CCL	TCC	I2S	IOSET	Power Rail	Reset State
1	PA00 / XIN32	EXTINT[0]				XY[0]		OANEG[1]			SERCOM1/ PAD[0]	6	TCC2/ WO[0]							AVDD	I/O, Hi-Z
2	PA01 / XOUT32	EXTINT[1]				XY[1]		OAPOS[1]			SERCOM1/ PAD[1]	6	TCC2/ WO[1]							AVDD	I/O, Hi-Z
3	PA02⁽³⁾⁽⁶⁾	EXTINT[2]		AIN[0]		XY[2]	VOUT0	OANEG[0]			SERCOM0/ PAD[2]	3					TCC3/ WO[0]			AVDD	I/O, Hi-Z
4	PA03	EXTINT[3]	VREFA	AIN[1]		XY[3]		OANEG[2]			SERCOM0/ PAD[3]	3					TCC3/ WO[1]			AVDD	I/O, Hi-Z
5	AVSS
6	AVDD
7	PB08	EXTINT[8]		AIN[18]		XY[20]					SERCOM3/ PAD[0]	4	TC0/ WO[0]			IN[8]	TCC3/ WO[6]			AVDD	I/O, Hi-Z
8	PB09	EXTINT[9]		AIN[19]		XY[21]					SERCOM3/ PAD[1]	4	TC0/ WO[1]			OUT[2]	TCC3/ WO[7]			AVDD	I/O, Hi-Z
9	PA04	EXTINT[4]	VREFB	AIN[2]	AIN[0]			OAOUT[2]			SERCOM0/ PAD[0]	3	TCC0/ WO[0]			IN[0]	TCC3/ WO[2]			AVDD	I/O, Hi-Z
10	PA05	EXTINT[5]		AIN[3]	AIN[1]	XY[4]		OAPOS[2]			SERCOM0/ PAD[1]	3	TCC0/ WO[1]			IN[1]	TCC3/ WO[3]			AVDD	I/O, Hi-Z
11	PA06	EXTINT[6]		AIN[4]	AIN[2]	XY[5]		OAPOS[0]			SERCOM0/ PAD[2]	3	TCC1/ WO[0]			IN[2]	TCC3/ WO[4]			AVDD	I/O, Hi-Z
12	PA07⁽³⁾	EXTINT[7]		AIN[5]	AIN[3]		VOUT1	OAOUT[0]			SERCOM0/ PAD[3]	3	TCC1/ WO[1]			OUT[0]	TCC3/ WO[5]			AVDD	I/O, Hi-Z
13	PA08	NMI		AIN[6]		XY[6]			SERCOM1/ PAD[0]	1	SERCOM2/ PAD[0]	2	TCC0/ WO[0]	RTC/ IN[0]		IN[3]	TCC1/ WO[2]	SDI	1	VDD	I/O, Hi-Z
14	PA09	EXTINT[0]		AIN[7]		XY[7]			SERCOM1/ PAD[1]	1	SERCOM2/ PAD[1]	2	TCC0/ WO[1]	RTC/ IN[1]		IN[4]	TCC1/ WO[3]	MCK[0]	1,2	VDD	I/O, Hi-Z
15	PA10	EXTINT[1]		AIN[8]		XY[8]			SERCOM1/ PAD[2]	1, 6	SERCOM2/ PAD[2]	2	TCC1/ WO[0]		GCLK/ IO[4]	IN[5]	TCC0/ WO[2]	SCK[0]	1	VDD	I/O, Hi-Z
16	PA11	EXTINT[2]		AIN[9]		XY[9]			SERCOM1/ PAD[3]	1, 6	SERCOM2/ PAD[3]	2	TCC1/ WO[1]		GCLK/ IO[3]	OUT[1]	TCC0/ WO[3]	FS[0]	2	VDD	I/O, Hi-Z
17	AVSSPLL
18	VDD
19	VSS
20	VDDPLL
21	PA12	EXTINT[12]				XY[24]			SERCOM2/ PAD[0]	1	SERCOM4/ PAD[0]	2	TCC2/ WO[0]		AC/ CMP[0]		TCC0/ WO[6]			VDD	I/O, Hi-Z
22	PA13	EXTINT[13]				XY[25]			SERCOM2/ PAD[1]	1	SERCOM4/ PAD[1]	2	TCC2/ WO[1]		AC/ CMP[1]		TCC0/ WO[7]			VDD	I/O, Hi-Z
23	PA14 / XIN	EXTINT[3]				XY[10]			SERCOM2/ PAD[2]	1	SERCOM0/ PAD[2]	4	TC0/ WO[0]		GCLK/ IO[0]		TCC0/ WO[4]			VDD	I/O, Hi-Z
24	PA15 / XOUT	EXTINT[4]				XY[11]			SERCOM2/ PAD[3]	1	SERCOM0/ PAD[3]	4	TC0/ WO[1]		GCLK/ IO[1]		TCC0/ WO[5]			VDD	I/O, Hi-Z
25	PA16	EXTINT[5]				XY[12]			SERCOM1/ PAD[0]	3	SERCOM0/ PAD[0]	4	TCC2/ WO[0]	RTC/ IN[2]	GCLK/ IO[2]	IN[0]	TCC0/ WO[6]			VDD	I/O, Hi-Z
26	PA17	EXTINT[6]				XY[13]			SERCOM1/ PAD[1]	3	SERCOM0/ PAD[1]	4	TCC2/ WO[1]	RTC/ IN[3]	GCLK/ IO[3]	IN[1]	TCC0/ WO[7]			VDD	I/O, Hi-Z
27	PA18	EXTINT[7]				XY[14]			SERCOM1/ PAD[2]	3	SERCOM0/ PAD[2]	4	TC2/ WO[0]	RTC/ OUT[0]	AC/ CMP[0]	IN[2]	TCC0/ WO[2]	FS[0]	1	VDD	I/O, Hi-Z
28	PA19	EXTINT[0]				XY[15]			SERCOM1/ PAD[3]	3	SERCOM0/ PAD[3]	4	TC2/ WO[1]	RTC/ OUT[1]	AC/ CMP[1]	OUT[0]	TCC0/ WO[3]	SDO	1,2	VDD	I/O, Hi-Z
29	PA20	EXTINT[4]				XY[22]			SERCOM3/ PAD[2]	3	SERCOM2/ PAD[2]	3	TC1/ WO[0]		GCLK/ IO[4]	IN[5]	TCC0/ WO[6]	SCK[0]	2	VDD	I/O, Hi-Z
30	PA21	EXTINT[5]				XY[23]			SERCOM3/ PAD[3]	3	SERCOM2/ PAD[3]	3			GCLK/ IO[5]		TCC0/ WO[7]	SCK[1]	1,2	VDD	I/O, Hi-Z
31	PA22	EXTINT[1]				XY[16]			SERCOM0/ PAD[0]	1	SERCOM2/ PAD[0]	3	TC0/ WO[0]	RTC/ OUT[2]	GCLK/ IO[2]	IN[6]	TCC0/ WO[4]			VDD	I/O, Hi-Z
32	PA23	EXTINT[2]				XY[17]			SERCOM0/ PAD[1]	1	SERCOM2/ PAD[1]	3	TC0/ WO[1]	RTC/ OUT[3]	GCLK/ IO[1]	IN[7]	TCC0/ WO[5]			VDD	I/O, Hi-Z
33	PA24	EXTINT[3]							SERCOM0/ PAD[2]	1	SERCOM2/ PAD[2]	3	TC1/ WO[0]	USB/ DM	AC/ CMP[2]	IN[8]	TCC1/ WO[2]			VDD	I/O, Hi-Z
34	PA25	EXTINT[4]							SERCOM0/ PAD[3]	1	SERCOM2/ PAD[3]	3	TC1/ WO[1]	USB/ DP	AC/ CMP[3]	OUT[2]	TCC1/ WO[3]			VDD	I/O, Hi-Z
35	VSS
36	VDD
37	PB22	EXTINT[6]							SERCOM0/ PAD[2]	1	SERCOM5/ PAD[2]	4		USB/ SOF_1KHZ	GCLK/ IO[0]	IN[0]	TCC3/ WO[0]			VDD	I/O, Hi-Z
38	PB23	EXTINT[7]							SERCOM0/ PAD[3]	1	SERCOM5/ PAD[3]	4			GCLK/ IO[1]	OUT[0]	TCC3/ WO[1]			VDD	I/O, Hi-Z
39	VSS
40	RESET																			VDD	I, PU
41	VDDCORE
42	VSSCORE
43	VDDOUT
44	VDD
45	PA30 / SWCLK	EXTINT[6]				XY[18]							TCC1/ WO[0]	SWCLK	GCLK/ IO[0]	IN[3]	TCC3/ WO[4]			VDD	SWCLK, I, PU
46	PA31 / SWDIO	EXTINT[7]				XY[19]							TCC1/ WO[1]			OUT[1]	TCC3/ WO[5]			VDD	I/O, Hi-Z
47	PB02	EXTINT[2]		AIN[10]	AIN[4]				SERCOM3/ PAD[0]	3	SERCOM5/ PAD[0]	4	TC2/ WO[0]			OUT[0]	TCC3/ WO[2]			VDD	I/O, Hi-Z
48	PB03⁽⁶⁾	EXTINT[3]		AIN[11]	AIN[5]				SERCOM3/ PAD[1]	3	SERCOM5/ PAD[1]	4	TC2/ WO[1]				TCC3/ WO[3]			VDD	I/O, Hi-Z
Note: All analog pin functions are on the peripheral function B. The peripheral function B must be selected to disable the digital control of the pin. Refer to TCC peripheral chapter for the list of supported features for each peripheral instance. When DAC0 or DAC1 channel is enabled, respective VOUT0 (PA02) or VOUT1 (PA07) pins cannot be used for other purposes (excluding analog inputs). I²C is not supported on all SERCOM pins. Refer to SERCOM I²C peripheral chapter for the list of supported features for each peripheral instance. SERCOM1 signals are not available for the PIC32CM LS60 family as reserved for ATECC608B interconnection. The transition time of the following pins must be greater than 50μs in order to not affect the XOSC32 cycle to cycle jitter.