4.1 32-pin VQFN and 32-pin TQFP


32-pin VQFN and 32-pin TQFP (Top View)⁽¹⁾
PIC32CM1216(LE00/LS00)032

Note:

The 32-pin VQFN package has wettable flanks.

Table 4-1. 32-pin VQFN and 32-pin TQFP I/O Pinmux
Pin	Pin Name	A	B^(1,2)						C⁽³⁾		D⁽³⁾		E	G	H	I	Power Rail	Reset State
VQFN32 / TQFP32	Pin Name	EIC	REF	ADC	AC	PTC	DAC	OPAMP	SERCOM	IOSET	SERCOM ALT	IOSET	TC	RTC / USB / Debug	AC / GCLK	CCL	Power Rail	Reset State
1	PA00 / XIN32	EXTINT[0]				XY[0]		OANEG[1]			SERCOM1/ PAD[0]	2					AVDD	I/O, Hi-Z
2	PA01 / XOUT32	EXTINT[1]				XY[1]		OAPOS[1]			SERCOM1/ PAD[1]	2					AVDD	I/O, Hi-Z
3	PA02⁽²⁾⁽⁴⁾	EXTINT[2]		AIN[0]		XY[2]	VOUT0	OANEG[0]			SERCOM0/ PAD[2]	2					AVDD	I/O, Hi-Z
4	PA03	EXTINT[3]	VREFA	AIN[1]		XY[3]		OANEG[2]			SERCOM0/ PAD[3]	2					AVDD	I/O, Hi-Z
5	PA04	EXTINT[4]	VREFB	AIN[2]	AIN[0]			OAOUT[2]			SERCOM0/ PAD[0]	2				IN[0]	AVDD	I/O, Hi-Z
6	PA05	EXTINT[5]		AIN[3]	AIN[1]	XY[4]		OAPOS[2]			SERCOM0/ PAD[1]	2				IN[1]	AVDD	I/O, Hi-Z
7	PA06	EXTINT[6]		AIN[4]	AIN[2]	XY[5]		OAPOS[0]			SERCOM0/ PAD[2]	2				IN[2]	AVDD	I/O, Hi-Z
8	PA07⁽²⁾	EXTINT[7]		AIN[5]	AIN[3]		VOUT1	OAOUT[0]			SERCOM0/ PAD[3]	2				OUT[0]	AVDD	I/O, Hi-Z
9	AVDD
10	VSS
11	PA08	NMI		AIN[6]		XY[6]			SERCOM1/ PAD[0]	1	SERCOM2/ PAD[0]	2		RTC/ IN[0]		IN[3]	VDD	I/O, Hi-Z
12	PA09	EXTINT[0]		AIN[7]		XY[7]			SERCOM1/ PAD[1]	1	SERCOM2/ PAD[1]	2		RTC/ IN[1]		IN[4]	VDD	I/O, Hi-Z
13	PA10	EXTINT[1]		AIN[8]		XY[8]			SERCOM1/ PAD[2]	1, 2	SERCOM2/ PAD[2]	2			GCLK/ IO[4]	IN[5]	VDD	I/O, Hi-Z
14	VDDPLL
15	PA14 / XIN	EXTINT[3]				XY[10]			SERCOM2/ PAD[2]	1	SERCOM0/ PAD[2]	3	TC0/ WO[0]		GCLK/ IO[0]		VDD	I/O, Hi-Z
16	PA15 / XOUT	EXTINT[4]				XY[11]			SERCOM2/ PAD[3]	1	SERCOM0/ PAD[3]	3	TC0/ WO[1]		GCLK/ IO[1]		VDD	I/O, Hi-Z
17	PA16	EXTINT[5]				XY[12]			SERCOM1/ PAD[0]	3	SERCOM0/ PAD[0]	3		RTC/ IN[2]	GCLK/ IO[2]	IN[0]	VDD	I/O, Hi-Z
18	PA17	EXTINT[6]				XY[13]			SERCOM1/ PAD[1]	3	SERCOM0/ PAD[1]	3		RTC/ IN[3]	GCLK/ IO[3]	IN[1]	VDD	I/O, Hi-Z
19	PA18	EXTINT[7]				XY[14]			SERCOM1/ PAD[2]	3	SERCOM0/ PAD[2]	3	TC2/ WO[0]	RTC/ OUT[0]	AC/ CMP[0]	IN[2]	VDD	I/O, Hi-Z
20	PA19	EXTINT[0]				XY[15]			SERCOM1/ PAD[3]	3	SERCOM0/ PAD[3]	3	TC2/ WO[1]	RTC/ OUT[1]	AC/ CMP[1]	OUT[0]	VDD	I/O, Hi-Z
21	PA22	EXTINT[1]				XY[16]			SERCOM0/ PAD[0]	1	SERCOM2/ PAD[0]	3	TC0/ WO[0]	RTC/ OUT[2]	GCLK/ IO[2]		VDD	I/O, Hi-Z
22	PA23	EXTINT[2]				XY[17]			SERCOM0/ PAD[1]	1	SERCOM2/ PAD[1]	3	TC0/ WO[1]	RTC/ OUT[3]	GCLK/ IO[1]		VDD	I/O, Hi-Z
23	PA24	EXTINT[3]							SERCOM0/ PAD[2]	1	SERCOM2/ PAD[2]	3	TC1/ WO[0]	USB/ DM			VDD	I/O, Hi-Z
24	PA25	EXTINT[4]							SERCOM0/ PAD[3]	1	SERCOM2/ PAD[3]	3	TC1/ WO[1]	USB/ DP			VDD	I/O, Hi-Z
25	VSS
26	RESET																VDD	I, PU
27	VDDCORE
28	VSSCORE
29	VDDOUT
30	VDD
31	PA30 / SWCLK	EXTINT[6]				XY[18]					SERCOM1/ PAD[2]	2		SWCLK	GCLK/ IO[0]	IN[3]	VDD	SWCLK, I, PU
32	PA31 / SWDIO⁽⁴⁾	EXTINT[7]				XY[19]					SERCOM1/ PAD[3]	2				OUT[1]	VDD	I/O, Hi-Z
Note: All analog pin functions are on the peripheral function B. The peripheral function B must be selected to disable the digital control of the pin. When DAC0 or DAC1 channel is enabled, respective VOUT0 (PA02) or VOUT1 (PA07) pins cannot be used for other purposes (excluding analog inputs). I²C is not supported on all SERCOM pins. Refer to SERCOM I²C peripheral chapter for the list of supported features for each peripheral instance. The transition time of the following pins must be greater than 50μs in order to not affect the XOSC32 cycle to cycle jitter.