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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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Product Pages
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3
Memories
3.2
External Bus Interface (EBI)
3.2.5
Application Examples
3.2.5.4
Implementation Examples
3.2.5.4.1
1x16-bit DDR2 on EBI NCS1
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.2.1
Description
3.2.2
Embedded Characteristics
3.2.3
EBI Block Diagram
3.2.4
I/O Lines Description
3.2.5
Application Examples
3.2.5.1
Hardware Interface
3.2.5.2
Product Dependencies
3.2.5.3
Functional Description
3.2.5.4
Implementation Examples
3.2.5.4.1
1x16-bit DDR2 on EBI NCS1
3.2.5.4.1.1
Hardware Configuration
3.2.5.4.1.2
Software Configuration
3.2.5.4.2
Additional 1.8V 8-bit NAND Flash on NCS2 with NFD0_ON_D16 = 0, with DDR2-SDRAM
3.2.5.4.3
16-bit DDR2/3L on NCS1 and 8-bit NAND Flash on NCS2 with NFD0_ON_D16 = 1 (1.8V or 3.3V)
3.2.5.4.4
NOR Flash on NCS0
3.2.5.4.5
Device (FPGA, Static Memory, etc.) on NCS0, DDR on NCS1 and NAND Flash on NCS2
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.2.5.4.1 1x16-bit DDR2 on EBI NCS1
