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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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Product Pages
SAM9X70
SAM9X72
SAM9X75
Home
2
CPU and Interconnect
2.5
Boot Strategies
2.5.1
Standard Boot Strategy
2.5.1.4
Boot Configuration
2.5.1.4.7
Detailed Memory Boot Procedures
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Arm926EJ-S Processor
2.2
Debug and Test
2.3
Bus Matrix (MATRIX)
2.4
DMA Controller (XDMAC)
2.5
Boot Strategies
2.5.1
Standard Boot Strategy
2.5.1.1
Description
2.5.1.2
Flow Diagram
2.5.1.3
Chip Setup
2.5.1.4
Boot Configuration
2.5.1.4.1
Default Boot Sequence
2.5.1.4.2
Using a Boot Configuration Packet
2.5.1.4.3
Boot Sequence Controller Configuration Register
Boot Sequence Controller Configuration Register
2.5.1.4.4
Boot Configuration Packet
2.5.1.4.5
NVM Boot Sequence
2.5.1.4.6
Valid Code Detection
2.5.1.4.7
Detailed Memory Boot Procedures
2.5.1.4.7.1
NAND Flash Boot: NAND Flash Detection
2.5.1.4.7.2
NAND Flash Boot: PMECC Error Detection and Correction
2.5.1.4.8
SD Card/e.MMC Boot
2.5.1.4.9
SPI Flash Boot
2.5.1.4.10
QSPI NOR Flash Boot
2.5.1.5
SAM-BA Monitor
2.5.2
Secure Boot Strategy
2.5.3
Software Considerations
2.5.4
Hardware Considerations
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
2.5.1.4.7 Detailed Memory Boot Procedures
