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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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5
Image Subsystem
5.4
2D Graphics Engine (GFX2D)
5.4.4
Functional Description
5.4.4.2
GFX2D Surface Memory Format
5.4.4.2.1
Source Surface Memory Format
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
5.1
Overview
5.2
LCD Controller (LCDC)
5.3
Low Voltage Differential Signaling Controller (LVDSC)
5.4
2D Graphics Engine (GFX2D)
5.4.1
Description
5.4.2
Embedded Characteristics
5.4.3
Block Diagram
5.4.4
Functional Description
5.4.4.1
Ring Buffer Management
5.4.4.2
GFX2D Surface Memory Format
5.4.4.2.1
Source Surface Memory Format
5.4.4.2.1.1
4-bit Alpha Channel with 4-bit Indexed Color
5.4.4.2.1.2
8-bit Alpha Channel
5.4.4.2.1.3
8-bit Indexed Color
5.4.4.2.1.4
8-bit Alpha Channel with 8-bit Indexed Color
5.4.4.2.1.5
12-bpp Memory Mapping, RGB 4:4:4
5.4.4.2.1.6
16-bpp Memory Mapping with 4-bit Alpha Channel, ARGB 4:4:4:4
5.4.4.2.1.7
16-bpp Memory Mapping with Transparency Bit, TRGB 5:5:5
5.4.4.2.1.8
16-bpp Memory Mapping with Transparency Bit, RGBT 5:5:5:1
5.4.4.2.1.9
16-bpp Memory Mapping with Alpha Channel, RGB 5:6:5
5.4.4.2.1.10
32-bpp Memory Mapping, ARGB 8:8:8:8
5.4.4.2.1.11
32-bpp Memory Mapping, RGBA 8:8:8:8
5.4.4.2.2
Destination Surface Memory Format
5.4.4.2.3
Color Look-Up Table (CLUT)
5.4.4.3
GFX2D Visible Registers
5.4.4.4
Traffic Balancing Using Outstanding Regulation
5.4.4.5
Data Flow Instructions
5.4.4.6
Graphics Instructions
5.4.5
Register Summary
5.5
Display Serial Interface (DSI)
5.6
Camera Serial Interface (CSI)
5.7
CSI-2 Demultiplexer Controller (CSI2DC)
5.8
Image Sensor Controller (ISC)
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
5.4.4.2.1 Source Surface Memory Format
