18.3.1 Matrix Hosts
The H64MX manages 12 hosts, which means that each host can perform an access, concurrently with others, to an available client.
This matrix operates at MCK.
Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.
| Host No. | Name | Security Type |
|---|---|---|
| 0 | Bridge from system bus Matrix (Core) | Not applicable |
| 1, 2 | DMA Controller 0 | Peripheral Securable |
| 3, 4 | DMA Controller 1 | Peripheral Securable |
| 5, 6 | LCDC DMA | Peripheral Securable |
| 7 | SDMMC0 | Peripheral Securable |
| 8 | SDMMC1 | Peripheral Securable |
| 9 | ISC DMA | Peripheral Securable |
| 10 | AESB | Not applicable(1) |
| 11 | Bridge from H32MX to H64MX | Not applicable |
Note:
- Host signals secure/not secure are propagated through the AES bridge.