48.8.12 SPI Chip Select Register
This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.
SPI_CSRx must be written even if the user wants to use the default reset values. The BITS field is not updated with the translated value unless the register is written.
Name: | SPI_CSRx |
Offset: | 0x30 + x*0x04 [x=0..3] |
Reset: | 0 |
Property: | R/W |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DLYBCT[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DLYBS[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SCBR[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BITS[3:0] | CSAAT | CSNAAT | NCPHA | CPOL | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:24 – DLYBCT[7:0] Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT = 0, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
Otherwise, the following equations determine the delay:
If SPI_MR.BRSRCCLK = 0: DLYBCT = Delay Between Consecutive Transfers × fperipheral clock / 32
If SPI_MR.BRSRCCLK = 1: DLYBCT = Delay Between Consecutive Transfers × fGCLK / 32
Bits 23:16 – DLYBS[7:0] Delay Before SPCK
This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition.
When DLYBS = 0, the delay is half the SPCK clock period.
Otherwise, the following equations determine the delay:
If SPI_MR.BRSRCCLK = 0: DLYBS = Delay Before SPCK × fperipheral clock
If SPI_MR.BRSRCCLK = 1: DLYBS = Delay Before SPCK × fGCLK
Bits 15:8 – SCBR[7:0] Serial Clock Bit Rate
In Host mode, the SPI Interface uses a modulus counter to derive the SPCK bit rate from the clock defined by SPI_MR.BRSRCCLK bit. The bit rate is selected by writing a value from1 to 255 in the SCBR field. The following equations determine the SPCK bit rate:
If SPI_MR.BRSRCCLK = 0: SCBR = fperipheral clock / SPCK Bit Rate
If SPI_MR.BRSRCCLK = 1: SCBR = fGCLK / SPCK Bit Rate
Programming the SCBR field to 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
If SPI_MR.BRSRCCLK = 1, SCBR must be programmed with a value greater than 1.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Bits 7:4 – BITS[3:0] Bits Per Transfer
(See Note under the register table in SPI Chip Select Register.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
Value | Name | Description |
---|---|---|
0 | 8_BIT | 8 bits for transfer |
1 | 9_BIT | 9 bits for transfer |
2 | 10_BIT | 10 bits for transfer |
3 | 11_BIT | 11 bits for transfer |
4 | 12_BIT | 12 bits for transfer |
5 | 13_BIT | 13 bits for transfer |
6 | 14_BIT | 14 bits for transfer |
7 | 15_BIT | 15 bits for transfer |
8 | 16_BIT | 16 bits for transfer |
9 | – | Reserved |
10 | – | Reserved |
11 | – | Reserved |
12 | – | Reserved |
13 | – | Reserved |
14 | – | Reserved |
15 | – | Reserved |
Bit 3 – CSAAT Chip Select Active After Transfer
Value | Description |
---|---|
0 | The Peripheral Chip Select Line rises as soon as the last transfer is achieved. |
1 | The Peripheral Chip Select Line does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. |
Bit 2 – CSNAAT Chip Select Not Active After Transfer (ignored if CSAAT = 1)
Value | Description |
---|---|
0 | The Peripheral Chip Select Line does not rise between two transfers if SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same chip select. |
1 | The Peripheral Chip Select Line rises systematically after each transfer performed on the same client. It remains inactive after the end of transfer for a minimal duration of: If SPI_MR.BRSRCCLK = 0: If SPI_MR.BRSRCCLK = 1: If field DLYBCS is lower than 6, a minimum of six periods is introduced. |
Bit 1 – NCPHA Clock Phase
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between host and client devices.
Value | Description |
---|---|
0 | Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. |
1 | Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. |
Bit 0 – CPOL Clock Polarity
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between host and client devices.
Value | Description |
---|---|
0 | The inactive state value of SPCK is logic level zero. |
1 | The inactive state value of SPCK is logic level one. |