48.8.2 SPI Mode Register
This register can only be written if the WPEN bit is cleared in theSPI Write Protection Mode Register .
Name: | SPI_MR |
Offset: | 0x04 |
Reset: | 0x0 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DLYBCS[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PCS[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CMPMODE | LSBHALF | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
LLB | WDRBT | MODFDIS | BRSRCCLK | PCSDEC | PS | MSTR | |||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:24 – DLYBCS[7:0] Delay Between Chip Selects
This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is lower than 6, six peripheral clock periods are inserted by default.
Otherwise, the following equations determine the delay:
If BRSRCCLK = 0:
If BRSRCCLK = 1:
Bits 19:16 – PCS[3:0] Peripheral Chip Select
This field is only used if fixed peripheral select is active (PS = 0).
If SPI_MR.PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If SPI_MR.PCSDEC = 1:
NPCS[3:0] output signals = PCS.
Bit 12 – CMPMODE Comparison Mode
Value | Name | Description |
---|---|---|
0 | FLAG_ONLY | Any character is received and comparison function drives CMP flag. |
1 | START_CONDITION | Comparison condition must be met to start reception of all incoming characters until REQCLR is set. |
Bit 8 – LSBHALF LSB Timing Selection
Value | Description |
---|---|
0 | To be used only if SPI client LSB timing is 100% compliant with SPI standard (LSB duration is a full bit time). This value gives the better margin for SPI client response delay (less than 1 SPCK clock cycle). |
1 | To be selected if the SPI client LSB timing does not behave as the SPI standard (not triggered by NPCS deassertion in mode), the client response delay is limited to less than 1/2 SPCK cycle. |
Bit 7 – LLB Local Loopback Enable
LLB controls the local loopback on the data shift register for testing in Host mode only (MISO is internally connected on MOSI).
Value | Description |
---|---|
0 | Local loopback path disabled. |
1 | Local loopback path enabled. |
Bit 5 – WDRBT Wait Data Read Before Transfer
Value | Description |
---|---|
0 | No Effect. In Host mode, a transfer can be initiated regardless of SPI_RDR state. |
1 | In Host mode, a transfer can start only if SPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. |
Bit 4 – MODFDIS Mode Fault Detection
Value | Description |
---|---|
0 | Mode fault detection enabled |
1 | Mode fault detection disabled |
Bit 3 – BRSRCCLK Bit Rate Source Clock
If bit BRSRCCLK = 1, the SCBR field in SPI_CSRx must be programmed with a value greater than 1.
0 (PERIPH_CLK): The peripheral clock is the source clock for the bit rate generation.
1 (GCLK): PMC GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
Bit 2 – PCSDEC Chip Select Decode
When PCSDEC = 1, up to 15 chip select signals can be generated with the four NPCS lines using an external 4-bit to 16-bit decoder. The chip select registers define the characteristics of the 15 chip selects, with the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
Value | Description |
---|---|
0 | The chip select lines are directly connected to a peripheral device. |
1 | The four NPCS chip select lines are connected to a 4-bit to 16-bit decoder. |
Bit 1 – PS Peripheral Select
Value | Description |
---|---|
0 | Fixed Peripheral Select |
1 | Variable Peripheral Select |
Bit 0 – MSTR Host/Client Mode
Value | Description |
---|---|
0 | SPI is in Client mode |
1 | SPI is in Host mode |