47.5.2.8 Receiver Time-out

The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the URXD line. When a time-out is detected, UART_SR.TIMEOUT rises and can generate an interrupt, thus indicating to the driver an end of frame.

The time-out delay period (during which the receiver waits for a new character) is programmed in the field TO of the Receiver Time-out register (UART_RTOR). If TO is written to 0, the Receiver Time-out is disabled and no time-out is detected. UART_SR.TIMEOUT remains at ‘0’. Otherwise, the receiver loads an 8-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, UART_SR.TIMEOUT rises. Then, the user can either:

  • stop the counter clock until a new character is received. This is performed by writing a ‘1’ to UART_CR.STTTO. In this case, the idle state on URXD before a new character is received does not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on URXD after a frame is received, or
  • obtain an interrupt while no character is received. This is performed by writing a ‘1’ to UART_CR.RETTO. If RETTO is performed, the counter starts counting down immediately from the TO value. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.

The figure below shows the block diagram of the Receiver Time-out feature.

Figure 47-9. Receiver Time-out Block Diagram

The table below gives the maximum time-out period for some standard baud rates.

Table 47-2. Maximum Time-out Period
Baud Rate (bit/s) Bit Time (μs) Time-out (μs)
600 1,667 425,085
1,200 833 212,415
2,400 417 106,335
4,800 208 53,040
9,600 104 26,520
14,400 69 17,595
19,200 52 13,260
28,800 35 8,925
38,400 26 6,630
56,000 18 4,590
57,600 17 4,335
200,000 5 1,275