36.34 Pulse Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
| Name: | HSMC_PULSEx |
| Offset: | 0x0704 + x*0x14 [x=0..3] |
| Reset: | 0x01010101 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NCS_RD_PULSE[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NRD_PULSE[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NCS_WR_PULSE[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NWE_PULSE[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
Bits 30:24 – NCS_RD_PULSE[6:0] NCS Pulse Length in READ Access
In READ mode, The NCS signal pulse length is defined as:
NCS pulse length = (256 * NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles.
Bits 22:16 – NRD_PULSE[6:0] NRD Pulse Length
The NRD signal pulse length is defined as:
NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles.
The NRD pulse width must be as least 1 clock cycle.
Bits 14:8 – NCS_WR_PULSE[6:0] NCS Pulse Length in WRITE Access
In Write access, The NCS signal pulse length is defined as:
NCS pulse length = (256 * NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles.
The NCS pulse must be at least one clock cycle.
Bits 6:0 – NWE_PULSE[6:0] NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256 * NWE_PULSE[6]+NWE_PULSE[5:0]) clock cycles.
The NWE pulse must be at least one clock cycle.