36.9 PMECC Configuration Register

Name: HSMC_PMECCFG
Offset: 0x070
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
    AUTO   SPAREEN 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
    NANDWR  PAGESIZE[1:0] 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
    SECTORSZ BCH_ERR[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 20 – AUTO Automatic Mode Enable

This bit is only relevant in NAND Read mode, when HSMC_PMECCFG.SPAREEN=0 and HSMC_CFG.RSPARE=1.

ValueDescription
0 Indicates that the ECC computation is not retrieved automatically and must be read via User mode.
1 Indicates that the ECC computation is retrieved automatically via Data mode.

Bit 16 – SPAREEN Spare Enable

For NAND write access:

0: The spare area is not protected by ECC.

1: The spare area is protected with the last sector of data.

For NAND read access:

0: The spare area is not protected by ECC.

1: The spare area contains protected data.

Bit 12 – NANDWR NAND Write Access

ValueDescription
0 NAND read access.
1 NAND write access.

Bits 9:8 – PAGESIZE[1:0] Number of Sectors in the Page

ValueNameDescription
0 PAGESIZE_1SEC 1 sector for main area (512 or 1024 bytes).
1 PAGESIZE_2SEC 2 sectors for main area (1024 or 2048 bytes).
2 PAGESIZE_4SEC 4 sectors for main area (2048 or 4096 bytes).
3 PAGESIZE_8SEC 8 sectors for main area (4096 or 8192 bytes).

Bit 4 – SECTORSZ Sector Size

ValueDescription
0 The ECC computation is based on a sector of 512 bytes.
1 The ECC computation is based on a sector of 1024 bytes.

Bits 2:0 – BCH_ERR[2:0] Error Correcting Capability

ValueNameDescription
0 BCH_ERR2 2 errors
1 BCH_ERR4 4 errors
2 BCH_ERR8 8 errors
3 BCH_ERR12 12 errors
4 BCH_ERR24 24 errors
5 BCH_ERR32 32 errors